VHSIC Description Language (VHDL) is outlined. VHDL is a proper notation meant to be used in all stages of the construction of digital platforms. since it is either computing device readable and human readable, it helps the advance verification, synthesis, and checking out of designs; the communique of layout information; and the upkeep, amendment, and procurement of undefined. Its fundamental audiences are the implementors of instruments assisting the language and the complex clients of the language.
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Extra info for 1076-2002 IEEE Standard VHDL Language Reference Manual
A value is said to belong to a subtype of a given type if it belongs to the type and satisﬁes the constraint; the given type is called the base type of the subtype. A type is a subtype of itself; such a subtype is said to be unconstrained (it corresponds to a condition that imposes no restriction). The base type of a type is the type itself. The set of operations deﬁned for a subtype of a given type includes the operations deﬁned for the type; however, the assignment operation to an object having a given subtype only assigns values that belong to the subtype.
IEEE Std 1076-2002 LANGUAGE REFERENCE MANUAL The identiﬁers and character literals listed by an enumeration type deﬁnition must be distinct within the enumeration type deﬁnition. Each enumeration literal is the declaration of the corresponding enumeration literal; for the purpose of determining the parameter and result type proﬁle of an enumeration literal, this declaration is equivalent to the declaration of a parameterless function whose designator is the same as the enumeration literal and whose result type is the same as the enumeration type.
If a designator appears at the end of a subprogram body, it must repeat the designator of the subprogram. It is an error if a variable declaration in a subprogram declarative part declares a shared variable. 2). The STRING value of the attribute may specify implementation-dependent information about the foreign subprogram. Foreign subprograms may have non-VHDL implementations. An implementation may place restrictions on the allowable modes, classes, and types of the formal parameters to a foreign subprogram; such restrictions may include restrictions on the number and allowable order of the parameters.
1076-2002 IEEE Standard VHDL Language Reference Manual